HC1S25 Datasheet, PDF (108/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
Figure 6–8. New Critical Path
Examining this new critical path placement, you can see that there is
room for further performance improvement through additional location
assignments. The current slowest path is 9.775 ns of delay. Manually
moving the LABs in this critical path and placing them between the M4K
and M512 endpoints, and subsequently recompiling, shows improved
results not only for this path, but for several other paths, as this path
contained a major timing bottleneck. The critical path between this start
and endpoint was reduced to 8.797 ns (Figure 6–9). However, the entire
design only improved to 100.30 MHz because other paths are now the
slowest paths in the design. This illustrates that fixing one major
bottleneck path can raise the entire design performance since one high
fanout node can affect multiple timing paths, as was the case in this
example.
6–20
Altera Corporation
September 2008