HC1S25 Datasheet, PDF (109/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
Figure 6–9. Improved Results
Conclusion
In summary, this design example started with 65.30 MHz in the Stratix
FPGA device, and was improved to 74.34 MHz. It was then taken from
the Stratix FPGA device compile and improved to 100.30 MHz in the
HardCopy Stratix design, for a performance improvement of 35%.
Using performance-optimization techniques specifically for HardCopy
Stratix devices can achieve significant performance improvement over
the Stratix FPGA prototype device. Many of these changes must be
incorporated up-front in the HARDCOPY_FPGA_PROTOTYPE so that
your design is properly prepared for performance improvement after
running the HardCopy Timing Optimization wizard.
The example discussed in this chapter demonstrates the process for
performance improvement and various features in the Quartus II
software available for use when optimizing your Stratix FPGA prototype
and HardCopy Stratix device. It also demonstrates the importance of
planning ahead for the HardCopy Stratix design implementation while
continuing to work in the HARDCOPY_FPGA_PROTOTYPE design if
you are going to seek performance improvement in the HardCopy Stratix
device.
Altera Corporation
September 2008
6–21