HC1S25 Datasheet, PDF (85/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Static Timing Analysis
Static Timing
Analysis
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In addition to performing timing analysis, the Quartus II software also
provides all of the requisite netlists and Tcl scripts to perform static timing
analysis (STA) using the Synopsys STA tool, PrimeTime. The following
files, necessary for timing analysis with the PrimeTime tool, are generated
by the HardCopy Files Wizard:
■ <project name>_hcpy.vo—Verilog HDL output format
■ <project name>_hpcy_v.sdo—Standard Delay Format Output File
■ <project name>_pt_hcpy_v.tcl—Tcl script
These files are available in the <project name>\hardcopy directory.
PrimeTime libraries for the HardCopy Stratix and Stratix devices are
included with the Quartus II software.
1 Use the HardCopy Stratix libraries for PrimeTime to perform
STA during timing analysis of designs targeted to
HARDCOPY_FPGA_PROTOTYPE device.
For more information about static timing analysis, refer to the Classic
Timing Analyzer and the Synopsys PrimeTime Support chapters in
volume 3 of the Quartus II Handbook.
Early Power
Estimation
You can use PowerPlay Early Power Estimation to estimate the amount of
power your HardCopy Stratix or HardCopy APEX device will consume.
This tool is available on the Altera website. Using the Early Power
Estimator requires some knowledge of your design resources and
specifications, including:
■ Target device and package
■ Clock networks used in the design
■ Resource usage for LEs, DSP blocks, PLL, and RAM blocks
■ High speed differential interfaces (HSDI), general I/O power
consumption requirements, and pin counts
■ Environmental and thermal conditions
HardCopy Stratix Early Power Estimation
The PowerPlay Early Power Estimator provides an initial estimate of I_CC
for any HardCopy Stratix device based on typical conditions. This
calculation saves significant time and effort in gaining a quick
understanding of the power requirements for the device. No stimulus
vectors are necessary for power estimation, which is established by the
clock frequency and toggle rate in each clock domain.
Altera Corporation
September 2008
5–23
Preliminary