HC1S25 Datasheet, PDF (94/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Using Design Space Explorer for HardCopy Stratix Designs
device. The dark blue rectangles shown in Figure 6–1 are the
user-assigned LogicLock regions that have fixed locations. In this
example, the design needed to be constrained by LogicLock regions first
inside the HARDCOPY_FPGA_PROTOTYPE with Reserve Unused
Logic turned off in Properties in LogicLock regions. This selection allows
the Quartus II software to isolate and compact the logic of these blocks in
the HARDCOPY_FPGA_PROTOTYPE such that the placement is tightly
controlled in the HardCopy Stratix device.
Figure 6–1. A Well Partitioned Design
In the example shown in Figure 6–1, once suitable locations were
identified for LogicLock regions, the LogicLock region properties were
changed from floating to locked. The Quartus II software can then
reproduce their placement in subsequent compilations, while focusing
attention on fixing other portions of the design.
Using Design
Space Explorer
for HardCopy
Stratix Designs
The DSE feature in the Quartus II software allows you to evaluate various
compilation settings to achieve the best results for your FPGA designs.
DSE can also be used in the HardCopy Stratix project after running the
HardCopy Timing Optimization wizard.
Only some of the DSE settings affect HardCopy Stratix designs because
HDL synthesis and physical optimization have been completed on the
FPGA. No logic restructuring can occur after using the HardCopy Timing
Optimization wizard. When you compile your design, the placement of
LABs is optimized in the HardCopy Stratix device. To access the DSE GUI
6–6
Altera Corporation
September 2008