HC1S25 Datasheet, PDF (39/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Table 4–32. Stratix Device Capacitance Note (5)
Symbol
Parameter
C_IOTB
C_IOLR
C _{CL KTB}
C _{CL KLR}
C _{CL KLR+}
Input capacitance on I/O pins in I/O banks 3, 4, 7,
and 8.
Input capacitance on I/O pins in I/O banks 1, 2, 5,
and 6, including high-speed differential receiver
and transmitter pins.
Input capacitance on top/bottom clock input pins:
CLK[4..7] and CLK[12..15].
Input capacitance on left/right clock inputs: CLK1,
CLK3, CLK8, CLK10.
Input capacitance on left/right clock inputs: CLK0,
CLK2, CLK9, and CLK11.
Minimum
Typical
11.5
8.2
11.5
7.8
4.4
Maximum Unit
pF
pF
pF
pF
pF
Notes to Tables 4–4 through 4–32:
(1) Drive strength is programmable according to values in the Stratix Architecture chapter of the Stratix Device
Handbook.
(2) When the tx_outclock port of the altlvds_tx megafunction is 717 MHz, V_{O D( m in )} = 235 mV on the output
clock pin.
(3) Pin pull-up resistance values will lower if an external source drives the pin higher than V_CCIO.
(4) V_REF specifies the center point of the switching range.
(5) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5 pF.
Power
Consumption
Altera offers two ways to calculate power for a design, the Altera^® web
power calculator and the power estimation feature in the Quartus^® II
software.
The interactive power calculator on the Altera website is typically used
prior to designing the FPGA in order to get a magnitude estimate of the
device power. The Quartus II software power estimation feature allows
designers to apply test vectors against their design for more accurate
power consumption modeling.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
Timing Closure
The timing numbers in Tables 4–34 to 4–43 are only provided as an
indication of allowable timing for HardCopy Stratix devices. The
Quartus II software provides preliminary timing information for
HardCopy Stratix designs, which can be used as an estimation of the
device performance.
Altera Corporation
September 2008
4–15