HC1S25 Datasheet, PDF (52/110 Pages) Altera Corporation – HardCopy Stratix Device Family

High-Speed I/O Specification
Table 4–48. HardCopy Stratix Maximum Output Clock Rate (Using I/O Pins)
for PLL[1, 2, 3, 4] Pins (Part 2 of 2)
I/O Standard
LVDS (2)
HyperTransport
technology (2)
Performance
Unit
717
MHz
420
MHz
Notes to Tables 4–47 through 4–48:
(1) Differential SSTL-2 outputs are only available on column clock pins.
(2) These parameters are only available on row I/O pins.
(3) SSTL-2 in maximum drive strength condition.
(4) SSTL-2 in minimum drive strength with ≤10pF output load condition.
(5) SSTL-2 in minimum drive strength with > 10pF output load condition.
(6) Differential SSTL-2 outputs are only supported on column clock pins.
High-Speed I/O
Specification
Table 4–49 provides high-speed timing specifications definitions.
Table 4–49. High-Speed Timing Specifications and Terminology
High-Speed Timing Specification
Terminology
t_C
f_HSCLK
t_RISE
t_FALL
Timing unit interval (TUI)
f_HSDR
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t_DUTY
t_LOCK
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = t_C/w).
Maximum LVDS data transfer rate (f_HSDR = 1/TUI).
The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS
measurement.
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t_SW (max) – t_SW (min).
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
4–28
Altera Corporation
September 2008