HC1S25 Datasheet, PDF (46/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
Tables 4–42 through 4–43 show the external timing parameters on column
and row pins for HC1S80 devices.
Table 4–42. HC1S80 External I/O Timing on Column Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
0.884
ns
0.000
ns
3.267
7.415
ns
3.207
7.291
ns
3.207
7.291
ns
0.506
ns
0.000
ns
1.635
2.828
ns
1.575
2.704
ns
1.575
2.704
ns
Table 4–43. HC1S80 External I/O Timing on Rows Using Pin Global Clock
Networks
Symbol
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
1.362
ns
0.000
ns
3.457
7.859
ns
3.484
7.927
ns
3.484
7.927
ns
0.994
ns
0.000
ns
1.821
3.254
ns
1.848
3.322
ns
1.848
3.322
ns
4–22
Altera Corporation
September 2008