HC1S25 Datasheet, PDF (50/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
4–26
Tables 4–47 through 4–48 show the maximum output clock rate for
column and row pins in HardCopy Stratix devices.
Table 4–47. HardCopy Stratix Maximum Output Clock Rate for PLL[5, 6, 11,
12] Pins (Part 1 of 2)
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I (3)
SSTL-2 class I (4)
SSTL-2 class I (5)
SSTL-2 class II (3)
SSTL-2 class II (4)
SSTL-2 class II (5)
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
Differential SSTL-2 (6)
LVPECL (2)
PCML (2)
Performance
350
350
250
225
350
200
200
200
200
200
200
150
200
200
150
150
150
250
225
250
225
350
350
350
350
350
200
225
200
500
350
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
September 2008