HC1S25 Datasheet, PDF (74/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Series Handbook, Volume 1
Design
Optimization
and
Performance
Estimation
■ quartus_sh --flow hardcopy_full_compile <project_name>
[-c <revision>] r
This command performs the following tasks:
■ Compiles the exsisting project for a
HARDCOPY_FPGA_PROTOTYPE device.
■ Migrates the project to a HardCopy Stratix project.
■ Opens the migrated HardCopy Stratix project and compiles it for a
HardCopy Stratix device.
The HardCopy Timing Optimization Wizard creates the HardCopy
Stratix project in the Quartus II software, where you can perform design
optimization and performance estimation of your HardCopy Stratix
device.
Design Optimization
Beginning with version 4.2, the Quartus II software supports HardCopy
Stratix design optimization by providing floorplans for placement
optimization and HardCopy Stratix timing models. These features allows
you to refine placement of logic array blocks (LAB) and optimize the
HardCopy design further than the FPGA performance. Customized
routing and buffer insertion done in the Quartus II software are then used
to estimate the design’s performance in the migrated device. The
HardCopy device floorplan, routing, and timing estimates in the
Quartus II software reflect the actual placement of the design in the
HardCopy Stratix device, and can be used to see the available resources,
and the location of the resources in the actual device.
Performance Estimation
Figure 5–5 illustrates the design flow for estimating performance and
optimizing your design. You can target your designs to
HARDCOPY_FPGA_PROTOTYPE devices, migrate the design to the
HardCopy Stratix device, and get placement optimization and timing
estimation of your HardCopy Stratix device.
In the event that the required performance is not met, you can:
■ Work to improve LAB placement in the HardCopy Stratix project.
or
5–12
Preliminary
Altera Corporation
September 2008