HC1S25 Datasheet, PDF (42/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
Tables 4–34 through 4–35 show the external timing parameters on column
and row pins for HC1S25 devices.
Table 4–34. HC1S25 External I/O Timing on Column Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
1.371
ns
0.000
ns
2.809
7.155
ns
2.749
7.040
ns
2.749
7.040
ns
1.271
ns
0.000
ns
1.124
2.602
ns
1.064
2.487
ns
1.064
2.487
ns
Table 4–35. HC1S25 External I/O Timing on Row Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Min
Max
1.665
0.000
2.834
2.861
2.861
1.538
0.000
1.164
1.191
1.191
7.194
7.276
7.276
2.653
2.735
2.735
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4–18
Altera Corporation
September 2008