HC1S25 Datasheet, PDF (70/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Series Handbook, Volume 1
Figure 5–2. Selecting a HARDCOPY_FPGA_PROTOTYPE Device
By choosing the HARDCOPY_FPGA_PROTOTYPE device, all the
design information, available resources, package option, and pin
assignments are constrained to guarantee a seamless migration of
your project to the HardCopy Stratix device. The netlist resulting
from the HARDCOPY_FPGA_PROTOTYPE device compilation
contains information about the electrical connectivity, resources
used, I/O placements, and the unused resources in the FPGA device.
4. On the Assignments menu, click Settings. In the Category list, select
HardCopy Settings and specify the input transition timing to be
modeled for both clock and data input pins. These transition times
are used in static timing analysis during back-end timing closure of
the HardCopy device.
5. Add constraints to your HARDCOPY_FPGA_PROTOTYPE device,
and on the Processing menu, click Start Compilation to compile the
design.
5–8
Preliminary
Altera Corporation
September 2008