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HC1S25 Datasheet, PDF (47/110 Pages) Altera Corporation – HardCopy Stratix Device Family | |||
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Operating Conditions
Maximum Input and Output Clock Rates
Tables 4â44 through 4â46 show the maximum input clock rate for column
and row pins in HardCopy Stratix devices.
Table 4â44. HardCopy Stratix Maximum Input Clock Rate for CLK[7..4] and
CLK[15..12] Pins
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1Ã
AGP 2Ã
CTT
Differential HSTL
LVPECL (1)
PCML (1)
LVDS (1)
HyperTransport
technology (1)
Performance
422
422
422
422
422
300
300
400
400
400
400
400
400
400
400
400
400
422
422
422
422
422
300
400
645
300
645
500
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
September 2008
4â23
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