HC1S25 Datasheet, PDF (98/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
Figure 6–3. HardCopy Stratix Device Floorplan with Soft Region On
To keep the LogicLock region contents bounded in the final placement in
the HardCopy Stratix device floorplan, turn off the Soft Region option.
After turning off the Soft Region option and compiling the HardCopy
Stratix design, the result is an f_MAX of 88.14 MHz—a gain of 33% over the
Stratix FPGA device performance. The bounded placement in the
LogicLock region helps to achieve performance improvement in
well-partitioned design blocks by taking advantage of the smaller die size
and custom metal routing interconnect of the HardCopy Stratix device.
The floorplan of the bounded LogicLock region is visible in Figure 6–4. In
this figure, you can see the difference in disabling the Soft Region setting
in the HardCopy Stratix design.
6–10
Altera Corporation
September 2008