HC1S25 Datasheet, PDF (75/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Optimization and Performance Estimation
■ Go back to the HARDCOPY_FPGA_PROTOTYPE project and
optimize that design, modify your RTL source code, repeat the
migration to the HardCopy Stratix device, and perform the
optimization and timing estimation steps.
1 On average, HardCopy Stratix devices are 40% faster than the
equivalent -6 speed grade Stratix FPGA device. These
performance numbers are highly design dependent, and you
must obtain final performance numbers from Altera.
Figure 5–5. Obtaining a HardCopy Performance Estimation
Proven Netlist,
Pin Assignments, & Timing
Constraints
Stratix FPGA
HardCopy Placement
& Timing Analysis
Timing
Met?
Proven Netlist & New
Timing & Placement
Constraint
Yes
HardCopy Stratix
No
To perform Timing Analysis for a HardCopy Stratix device, follow these
steps:
1. Open an existing project compiled for a
HARDCOPY_FPGA_PROTOYPE device.
2. On the Project menu, point to HardCopy Utilities and click
HardCopy Timing Optimization Wizard.
3. Select a destination directory for the migrated project and complete
the HardCopy Timing Optimization Wizard process.
On completion of the HardCopy Timing Optimization Wizard, the
destination directory created contains the Quartus II project file, and
all files required for HardCopy Stratix implementation. At this stage,
the design is copied from the HARDCOPY_FPGA_PROTOTYPE
project directory to a new directory to perform the timing analysis.
This two-project directory structure enables you to move back and
forth between the HARDCOPY_FPGA_PROTOTYPE design
database and the HardCopy Stratix design database. The Quartus II
software creates the <project name>_hardcopy_optimization
directory.
You do not have to select the HardCopy Stratix device while
performing performance estimation. When you run the HardCopy
Timing Optimization Wizard, the Quartus II software selects the
Altera Corporation
September 2008
5–13
Preliminary