HC1S25 Datasheet, PDF (60/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Document Revision History
The dashed line (Figure 4–4) shows the ESD current discharge path
during a negative voltage zap.
Figure 4–4. ESD Protection During Negative Voltage Zap
IO
Source
PMOS
Gate
N+ ^D
Drain
IO
Drain
P-Substrate
G
NMOS ^Gate
N+ ^S
Source
GND
GND
f
f
Details of ESD protection are also outlined in the Hot-Socketing and
Power-Sequencing Feature and Testing for Altera Devices white paper
located on the Altera website at www.altera.com.
For information on ESD results of Altera products, see the Reliability
Report on the Altera website at www.altera.com.
Document
Table 4–53 shows the revision history for this chapter.
Revision History
Table 4–53. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
September 2008
v3.4
Updated the revision history.
June 2007 v3.3
Updated R_CONF section of Table 4–3.
Added the “Electrostatic Discharge” section.
Summary of Changes
—
—
4–36
Altera Corporation
September 2008