EP2A15 Datasheet, PDF (98/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 77. APEX II Selectable I/O Standards Output Adder Delays
Symbol
-7 Speed Grade
-8 Speed Grade
-9 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
LVTTL
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
HSTL Class I
HSTL Class II
LVDS
LVPECL
PCML
CTT
3.3-V AGP 1×
3.3-V AGP 2×
HyperTransport
Differential
HSTL
0.00
0.00
3.32
2.65
1.20
− 0.68
− 0.68
− 0.45
− 0.52
− 0.52
− 0.68
− 0.81
− 0.08
− 0.23
− 1.41
− 1.38
− 1.30
0.00
0.00
0.00
− 1.22
− 1.41
0.00
0.00
3.82
3.05
1.38
− 0.78
− 0.78
− 0.52
− 0.60
− 0.60
− 0.78
− 0.93
− 0.09
− 0.27
− 1.62
− 1.58
− 1.50
0.00
0.00
0.00
− 1.41
− 1.62
0.00
ns
0.00
ns
4.20
ns
3.36
ns
1.52
ns
− 0.85
ns
− 0.85
ns
− 0.57
ns
− 0.66
ns
− 0.66
ns
− 0.86
ns
− 1.02
ns
− 0.10
ns
− 0.30
ns
− 1.79
ns
− 1.74
ns
− 1.65
ns
0.00
ns
0.00
ns
0.00
ns
− 1.55
ns
− 1.79
ns
Power
Consumption
Detailed power consumption information for APEX II devices will be
released via a future interactive power estimator on the Altera web site.
Device Pin-
Outs
See the Altera web site (http://www.altera.com) or the Altera Digital
Library for pin-out information.
98
Altera Corporation