EP2A15 Datasheet, PDF (7/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Each I/O pin is fed by an IOE located at the end of each row and column
of the FastTrack interconnect. Each IOE contains a bidirectional I/O buffer
and six registers that can be used for registering input, output, and
output-enable signals. When used with a dedicated clock pin, these
registers provide exceptional performance and interface support with
external memory devices such as DDR SDRAM and ZBT and QDR SRAM
devices.
IOEs provide a variety of features such as: 3.3-V, 64-bit, 66-MHz PCI
compliance, 3.3-V, 64-bit, 133-MHz PCI-X compliance, Joint Test Action
Group (JTAG) boundary-scan test (BST) support, output drive strength
control, slew-rate control, tri-state buffers, bus-hold circuitry,
programmable pull-up resistors, programmable input and output delays,
and open-drain outputs.
APEX II devices offer enhanced I/O support, including support for 1.5 V,
1.8 V, 2.5 V, 3.3 V, LVCMOS, LVTTL, HSTL, LVDS, LVPECL,
HyperTransport, PCML, 3.3-V PCI, PCI-X, GTL+, SSTL-2, SSTL-3, CTT,
and 3.3-V AGP I/O standards. High-speed (up to 1.0 Gbps) differential
transfers are supported with True-LVDS circuitry for LVDS, LVPECL,
HyperTransport, and PCML I/O standards. The optional CDS feature
corrects any clock-to-data skew at the True-LVDS receiver channels,
allowing for flexible board topologies. Up to 88 Flexible-LVDS channels
support differential transfer at up to 400 Mbps (DDR) for LVDS and
HyperTransport I/O standards.
An ESB can implement many types of memory, including Dual-Port+
RAM, CAM, ROM, and FIFO functions. Embedding the memory directly
into the die improves performance and reduces die area compared to
distributed-RAM implementations. The abundance of cascadable ESBs
ensures that the APEX II device can implement multiple wide memory
blocks for high-density designs. The ESB’s high speed ensures it can
implement small memory blocks without any speed penalty. The
abundance of ESBs, in conjunction with the ability for one ESB to
implement two separate memory blocks, ensures that designers can create
as many different-sized memory blocks as the system requires.
Figure 1 shows an overview of the APEX II device.
Altera Corporation
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