EP2A15 Datasheet, PDF (52/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 31. APEX II I/O Banks
I/O banks 1 and 2 support Flexible-LVDS,
HyperTransport, and LVPECL inputs, and
regular I/O pin standards.
I/O Bank 1
I/O Bank 2
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
(1)
I/O Bank 8
Regular I/O Pins Support
■ 3.3-V, 2.5-V, 1.8-V, and
1.5-V LVTTL
■ 3.3-V PCI and PCI-X
■ GTL+
■ AGP
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ HSTL Class I and II
■ CTT
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
(1)
I/O Bank 3
I/O Bank 7
(1)
True-LVDS, LVPECL,
PCML, and HyperTransport
Output Block (2)
Individual
Power Bus
I/O Bank 4
(1)
True-LVDS, LVPECL,
PCML, and HyperTransport
Input Block (2)
I/O Bank 6
I/O Bank 5
I/O banks 5 and 6 support Flexible-LVDS and
HyperTransport outputs and regular I/O pin standards.
Notes to Figure 31:
(1) For more information on placing I/O pins within LVDS blocks, refer to the “High-Speed Interface Pin Location”
section in Application Note 166 (Using High-Speed I/O Standards in APEX II Devices).
(2) If the True-LVDS pins or the Flexible-LVDS pins are not used for high-speed differential signalling, they can
support all of the I/O standards and can be used as input, output, or bidirectional pins with V_CCIO set to 3.3 V, 2.5 V,
1.8 V, or 1.5 V. However, True-LVDS pins do not support the HSTL Class II output.
Each I/O bank has its own VCCIO pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a different
standard independently. Each bank can also use a separate V_REF level to
support any one of the terminated standards (such as SSTL-3)
independently.
52
Altera Corporation