EP2A15 Datasheet, PDF (62/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
ClockShift Circuitry
General-purpose PLLs in APEX II devices have ClockShift circuitry that
provides programmable phase shift. Users can enter a phase shift (in
degrees or time units) that affects all PLL outputs. Phase shifts of 90°, 180°,
and 270° can be implemented exactly. Other values of phase shifting, or
delay shifting in time units, are allowed with a resolution range of 0.5 ns
to 1.0 ns. This resolution varies with frequency input and the user-entered
multiplication and division factors. The phase shift ability is only possible
on a multiplied or divided clock if the input and output frequency have
an integer multiple relationship (i.e., f_IN/f_OUT or f_OUT/f_IN must be an
integer).
Clock Enable Signal
APEX II PLLs have a CLKLK_ENA pin for enabling/disabling all device
PLLs. When the CLKLK_ENA pin is high, the PLL drives a clock to all its
output ports. When the CLKLK_ENA pin is low, the clock0, clock1, and
extclock ports are driven by GND and all of the PLLs go out of lock.
When the CLKLK_ENA pin goes high again, the PLL relocks.
The individual enable port for each PLL is programmable. If more than
one PLL is instantiated, each one does not have to use the clock enable. To
enable/disable the device PLLs with the CLKLK_ENA pin, the inclocken
port on the altclklock instance must be connected to the CLKLK_ENA
input pin.
SignalTap
Embedded
Logic Analyzer
Lock Signals
The APEX II device PLL circuits support individual LOCK signals. The
LOCK signal drives high when the PLL has locked onto the input clock.
LOCK remains high as long as the input remains within specification. It
will go low if the input is out of specification. A LOCK pin is optional for
each PLL used in the APEX II devices; when not used, they are I/O pins.
This signal is not available internally; if it is used in the logic array, it must
be fed back in with an input pin.
APEX II devices include device enhancements to support the SignalTap
embedded logic analyzer. By including this circuitry, the APEX II device
provides the ability to monitor design operation over a period of time
through the IEEE Std. 1149.1 (JTAG) circuitry; a designer can analyze
internal logic at speed without bringing internal signals to the I/O pins.
This feature is particularly important for advanced packages such as
FineLine BGA packages because adding a connection to a pin during the
debugging process can be difficult after a board is designed and
manufactured.
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Altera Corporation