EP2A15 Datasheet, PDF (11/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Dedicated
8
Clocks
Fast Global
4
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
SYNCLOAD
or LABCLKENA2
LABCLKENA1
LABCLR1 (1)
SYNCCLR
or LABCLK2 (2)
LABCLK1
LABCLR2 (1)
Notes to Figure 4:
(1) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(2) The SYNCCLR signal can be generated by the local interconnect or global signals.
Logic Element
The LE is the smallest unit of logic in the APEX II architecture. Each LE
contains a four-input LUT, which is a function generator that can quickly
implement any function of four variables. In addition, each LE contains a
programmable register and carry and cascade chains. Each LE drives the
local interconnect, MegaLAB interconnect, and FastTrack interconnect
routing structures. See Figure 5.
Altera Corporation
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