EP2A15 Datasheet, PDF (34/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Content-Addressable Memory
APEX II devices can implement CAM in ESBs. CAM can be thought of as
the inverse of RAM. RAM stores data in a specific location; when the
system submits an address, the RAM block provides the data. Conversely,
when the system submits data to CAM, the CAM block provides the
address where the data is found. For example, if the data FA12 is stored
in address 14, the CAM outputs 14 when FA12 is driven into it.
CAM is used for high-speed search operations. When searching for data
within a RAM block, the search is performed serially. Thus, finding a
particular data word can take many cycles. CAM searches all addresses in
parallel and outputs the address storing a particular word. When a match
is found, a match flag is set high. CAM is ideally suited for applications
such as Ethernet address lookup, data compression, pattern recognition,
cache tags, fast routing table lookup, and high-bandwidth address
filtering. Figure 21 shows the CAM block diagram.
Figure 21. CAM Block Diagram
data[ ]
wraddress[ ]
wren
inclock
inclocken
inaclr
data_address[ ]
match
outclock
outclocken
outaclr
The APEX II on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX II
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements a 32-word, 32-bit CAM. Wider
or deeper CAM, such as a 32-word, 64-bit or 128-word, 32-bit block, can
be implemented by combining multiple CAM blocks with some ancillary
logic implemented in LEs. The Quartus II software automatically
combines ESBs and LEs to create larger CAM blocks.
CAM supports writing “don’t care” bits into words of the memory. The
don’t-care bit can be used as a mask for CAM comparisons; any bit set to
don’t-care has no effect on matches.
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Altera Corporation