EP2A15 Datasheet, PDF (48/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 9. Programmable Drive Strength
I/O Standard
LVTTL (3.3 V)
LVTTL (2.5 V)
LVTTL (1.8 V)
LVTTL (1.5 V)
SSTL-3 class I and II
SSTL-2 class I and II
HSTL class I and II
GTL+ (3.3 V)
PCI
PCI-X
I_OH/I_OL Current Strength
Setting
4 mA
12 mA
24 mA (default)
2 mA
16 mA (default)
2 mA
8mA (default)
2 mA (default)
Minimum (default)
Open-Drain Output
APEX II devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each APEX II device I/O pin has a programmable
output slew rate control that can be configured for low-noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may introduce
noise transients into the system. A slow slew rate reduces system noise,
but adds a nominal delay to rising and falling edges. Each I/O pin has an
individual slew rate control, allowing the designer to specify the slew rate
on a pin-by-pin basis. The slew rate control affects both the rising and
falling edges.
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Altera Corporation