EP2A15 Datasheet, PDF (42/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 7. Peripheral Control Bus Destinations
Peripheral Bus
Output Enable 0 [OE0]
Output Enable 1 [OE1]
Output Enable 2 [OE2]
Output Enable 3 [OE3]
Output Enable 4 [OE4]
Output Enable 5 [OE5]
Clock Enable 0 [CE0]
Clock Enable 1 [CE1]
Clock Enable 2 [CE2]
Clock Enable 3 [CE3]
Clock Enable 4 [CE4]
Clock Enable 5 [CE5]
I/O Control Signal
OE
OE
OE
OE
OE
OE
CE, CLK
CE, OE
CE, CLK
CE, OE
CE, CLR
CE, CLR
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
fast global signals, or row global signals. Figure 28 shows the IOE in
bidirectional configuration.
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Altera Corporation