EP2A15 Datasheet, PDF (83/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 43. Dual-Port RAM Timing Microparameter Waveform
wrclock
wren
tESBWEH
wraddress
data-in
rdclock
rden
rdaddress
reg_data-out
unreg_data-out
an-1
an
din-1
tESBDATAH
din
tESBDATASU
a0
a1
a2
din0
din1
din2
tESBRESU
bn
doutn-2
doutn-1
tESBREH
b0
doutn-1
doutn
tESBSRC
b1
tESBDATACO1
doutn
tESBDATACO2
dout0
tESBWESU
tESBADDRSU
tESBADDRH
a3
a4
a5
din3
din4
din5
a6
din6
b2
b3
dout0
Table 49. APEX II f_MAX Routing Delays
Symbol
Parameter
t_F1-4
t_F5-20
t_F20+
Fan-out delay estimate using local interconnect; use to estimate routing delay for a signal
with fan-out of 1 to 4
Fan-out delay estimate using MegaLab interconnect; use to estimate routing delay for a
signal with fan-out of 5 to 20
Fan-out delay estimate using FastTrack interconnect; use to estimate routing delay for a
signal with fan-out greater than 20
Altera Corporation
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