EP2A15 Datasheet, PDF (33/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
In addition to the input/output mode clocking scheme, the clock
connections to the various ESB input/output registers are customizable in
the MegaWizard^® Plug-In Manager.
Single-Port Mode
The APEX II ESB also supports a single-port mode, which is used when
simultaneous reads and writes are not required. See Figure 20. A single
ESB can support up to two single-port mode RAMs.
Figure 20. ESB in Single-Port Mode
Dedicated Fast
Global Signals
Dedicated Clocks
Note (1)
8
4
data[ ]
DQ
ENA
address[ ]
wren
DQ
ENA
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
4,096 × 1
Data Out
Address
DQ
ENA
To FastTrack
Interconnect
outclken
Write Enable
inclken
inclock
outclock
DQ
ENA
Write
Pulse
Generator
Note to Figure 20:
(1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or chip-wide reset.
Altera Corporation
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