EP2A15 Datasheet, PDF (57/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 34. Multi-Bit CDS Supports N:1 Topology
Clock
APEX II
Device
APEX II
Device
Data
APEX II
Device
Data
Clock
Clock
APEX II
Device
Clock
When using multi-bit CDS, the J and W factors do not need to be the same
value. The byte boundary cannot be distinguished with multi-bit CDS
patterns (see Table 12). Therefore, the byte must be aligned using internal
logic. Table 12 shows the possible training patterns for multi-bit CDS.
Either pattern can be used.
Table 12. Multi-Bit CDS Patterns
W Factor
1, 2, 4 to 10
1, 2, 4 to 10
J Factor
4 to 10
4 to 10
Multi-Bit CDS Pattern
3 × J-bits of 010101 pattern
3 × J-bits of 101010 pattern
Pre-Programmed CDS
When the fixed clock-to-data skew is known, CDS can be pre-
programmed into the device during configuration. If CDS is pre-
programmed into the device, the training patterns do not need to be
transmitted to the receiver channels. The resolution of each pre-
programmed setting is 25% of the data period, to compensate for skew up
to ±50% of the data period.
Altera Corporation
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