EP2A15 Datasheet, PDF (43/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 28. APEX II IOE in Bidirectional I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
Output Clock
Enable Delay
Chip-Wide Reset
Logic Array
to Output
Register Delay
Input Clock
Enable Delay
OE Register
D
Q
ENA
CLRN/PRN
Output
t_ZX Delay
OE Register
t_CO Delay
VCCIO
Optional
PCI Clamp
VCCIO
Programmable
Pull-Up
Output Register
D
Q
Output
Pin
Delay
Drive Strength Control
ENA
CLRN/PRN
Open-Drain Output
Slew Control
Input Pin to
Logic Array Delay
Input Register
D
Q
Input Pin to
Input Register Delay
ENA
CLRN/PRN
Bus-Hold
Circuit
The APEX II IOE includes programmable delays that can be activated to
ensure zero hold times, minimum clock-to-output times, input IOE
register-to-logic array register transfers, or logic array-to-output IOE
register transfers.
Altera Corporation
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