EP2A15 Datasheet, PDF (13/99 Pages) Altera Corporation – Programmable Logic Device Family

Altera Corporation
APEX II Programmable Logic Device Family Data Sheet
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output. The APEX II
architecture provides two types of dedicated high-speed data paths that
connect adjacent LEs without using local interconnect paths: carry chains
and cascade chains. A carry chain supports high-speed arithmetic
functions such as counters and adders, while a cascade chain implements
wide-input functions such as equality comparators with minimum delay.
Carry and cascade chains connect LEs 1 through 10 in an LAB and all
LABs in the same MegaLAB structure.
Carry Chain
The carry chain provides a fast carry-forward function between LEs. The
carry-in signal from a lower-order bit drives forward into the higher-
order bit via the carry chain, and feeds into both the LUT and the next
portion of the carry chain. This feature allows the APEX II architecture to
implement high-speed counters, adders, and comparators of arbitrary
width. The Quartus II Compiler can create carry chain logic automatically
during the design process, or the designer can create it manually during
design entry. Parameterized functions such as DesignWare functions
from Synopsys and library of parameterized modules (LPM) functions
automatically take advantage of carry chains for the appropriate
functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain skips alternate LABs in a MegaLAB structure. A carry chain longer
than one LAB skips either from an even-numbered LAB to the next even-
numbered LAB, or from an odd-numbered LAB to the next odd-
numbered LAB. For example, the last LE of the first LAB in the upper-left
MegaLAB structure carries to the first LE of the third LAB in the
MegaLAB structure.
Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT and the carry chain
logic generates the carry-out signal, which is routed directly to the carry-
in signal of the next-higher-order bit. The final carry-out signal is routed
to an LE, where it is driven onto the local, MegaLAB, or FastTrack
interconnect routing structures.
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