EP2A15 Datasheet, PDF (61/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Note to Figure 35:
(1) n represents the prescale divider for the PLL input. m represents the multiplier. k and v represent the different post
scale dividers for the two possible PLL outputs. m and k are integers that range from 1 to 160. n and v are integers
that range from 1 to 16.
Altera Corporation
Advanced ClockBoost Multiplication & Division
APEX II PLLs include circuitry that provides clock synthesis for eight
internal outputs and two external outputs using m/(n × output divider)
scaling. When a PLL is locked, the locked output clock aligns to the rising
edge of the input clock. The closed loop equation for Figure 35 gives an
output frequency f_clock0 = (m/(n × k))f_IN and f_clock1 = (m/(n × v))f_IN. These
equations allow the multiplication or division of clocks by a
programmable number. The Quartus II software automatically chooses
the appropriate scaling factors according to the frequency, multiplication,
and division values entered.
A single PLL in an APEX II device allows for multiple user-defined
multiplication and division ratios that are not possible even with multiple
delay-locked loops (DLLs). For example, if a frequency scaling factor of
3.75 is needed for a given input clock, a multiplication factor of 15 and a
division factor of 4 can be entered. This advanced multiplication scaling
can be performed with a single PLL, making it unnecessary to cascade
PLL outputs.
External Clock Outputs
APEX II devices have two low-jitter external clocks available for external
clock sources. Other devices on the board can use these outputs as clock
sources.
There are three modes for external clock outputs.
■ Zero Delay Buffer: The external clock output pin is phase aligned
with the clock input pin for zero delay. Multiplication,
programmable phase shift, and time delay shift are not allowed in
this configuration. The MegaWizard interface for altclklock
should be used to verify possible clock settings.
■ External Feedback: The external feedback input pin is phase aligned
with clock input pin. By aligning these clocks, you can actively
remove clock delay and skew between devices. This mode has the
same restrictions as zero delay buffer mode.
■ Normal Mode: The external clock output pin will have phase delay
relative to the clock input pin. If an internal clock is used in this mode,
the IOE register clock will be phase aligned to the input clock pin.
Multiplication is allowed with the normal mode.
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