EP2A15 Datasheet, PDF (30/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
The ESB also enables variable width data ports for reading and writing to
the RAM ports in dual-port RAM configuration. For example, the ESB can
be written in 1× mode at port A while being read in 16× mode from port B.
Table 6 lists the supported variable width configurations for an ESB in
dual-port mode.
Table 6. Variable Width Configurations for Dual-Port RAM
Read Port Width
1 bit
2 bits, 4 bits, 8 bits, or 16 bits
Write Port Width
2 bits, 4 bits, 8 bits, or 16 bits
1 bit
ESBs can implement synchronous RAM, which is easier to use than
asynchronous RAM. A circuit using asynchronous RAM must generate
the RAM write enable (WE) signal while ensuring that its data and address
signals meet setup and hold time specifications relative to the WE signal.
In contrast, the ESB’s synchronous RAM generates its own WE signal and
is self-timed with respect to the global clock. Circuits using the ESB’s self-
timed RAM only need to meet the setup and hold time specifications of
the global clock.
ESB inputs are driven by the adjacent local interconnect, which in turn can
be driven by the MegaLAB or FastTrack interconnects. Because the ESB
can be driven by the local interconnect, an adjacent LE can drive it directly
for fast memory access. ESB outputs drive the MegaLAB and FastTrack
interconnects and the local interconnect for fast connection to adjacent LEs
or for fast feedback product-term logic.
When implementing memory, each ESB can be configured in any of the
following sizes: 512 × 8, 1,024 × 4, 2,048 × 2, or 4,096 × 1. For dual-port and
single-port modes, the ESB can be configured for 256 × 16 in addition to
the list above.
The ESB can also be split in half and used for two independent 2,048-bit
single-port RAM blocks. The two independent RAM blocks must have
identical configurations with a maximum width of 256 × 8. For example,
one half of the ESB can be used as a 256 × 8 single-port memory while the
other half is also used for a 256 × 8 single-port memory. This effectively
doubles the number of RAM blocks an APEX II device can implement for
its given number of ESBs. The Quartus II software automatically merges
two logical memory functions in a design into an ESB; the designer does
not need to merge the functions manually.
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