EP2A15 Datasheet, PDF (31/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
By combining multiple ESBs, the Quartus II software implements larger
memory blocks automatically. For example, two 256 × 16 RAM blocks can
be combined to form a 256 x 32 RAM block, and two 512 × 8 RAM blocks
can be combined to form a 512 × 16 RAM block. Memory performance
does not degrade for memory blocks up to 4,096 words deep. Each ESB
can implement a 4,096-word-deep memory; the ESBs are used in parallel,
eliminating the need for any external control logic that would increase
delays. To create a high-speed memory block more than 4,096-words
deep, the Quartus II software automatically combines ESBs with LE
control logic.
Input/Output Clock Mode
The ESB implements input/output clock mode for both dual-port and
bidirectional dual-port memory. An ESB using input/output clock mode
can use up to two clocks. On each of the two ports, A or B, one clock
controls all registers for inputs into the ESB: data input, WREN, read
address, and write address. The other clock controls the ESB data output
registers. Each ESB port, A or B, also supports independent read clock
enable, write clock enable, and asynchronous clear signals. Input/output
clock mode is commonly used for applications where the reads and writes
occur at the same system frequency, but require different clock enable
signals for the input and output registers. Figure 19 shows the ESB in
input/output clock mode.
Altera Corporation
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