EP2A15 Datasheet, PDF (32/99 Pages) Altera Corporation – Programmable Logic Device Family

Altera Corporation
32
Notes to Figure 19:
(1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.
(2) This configuration is not supported for bidirectional dual-port configuration.
APEX II Programmable Logic Device Family Data Sheet
Figure 19. ESB in Input/Output Clock Mode Note (1)