EP2A15 Datasheet, PDF (44/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input pin to logic array and IOE input register
delays. The Quartus II Compiler can program these delays automatically
to minimize setup time while providing a zero hold time. Delays are also
programmable for increasing the register to pin delays for output and/or
output enable registers. A programmable delay exists for increasing the
t_ZX delay to the output pin, which is required for ZBT interfaces. Table 8
shows the programmable delays for APEX II devices.
Table 8. APEX II Programmable Delay Chain
Programmable Delays
Input pin to logic array delay (1)
Input pin to input register delay
Output propagation delay
Output enable register t_CO delay
Output t_ZX delay
Output clock enable delay
Input clock enable delay
Logic array to output register delay
Note to Table 8:
(1) This delay has four settings: off and three levels of delay.
Quartus II Logic Option
Decrease input delay to internal cells
Decrease input delay to input register
Increase delay to output pin
Increase delay to output enable pin
Increase t_ZX delay to output pin
Increase output clock enable delay
Increase input clock enable delay
Decrease input delay to output register
The IOE registers in APEX II devices share the same source for clear or
preset. The designer can program preset and clear for each individual
IOE. The registers can be programmed to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device’s active-low input
upon power-up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that preset or clear signal.
Double Data Rate I/O
APEX II devices have six-register IOEs which support DDR interfacing by
clocking data on both positive and negative clock edges. The IOEs in
APEX II devices support DDR inputs, DDR outputs, and bidirectional
DDR modes.
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Altera Corporation