EP2A15 Datasheet, PDF (77/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 44. LVPECL Specifications Note (2)
Symbol
V_CCIO
V_IL
V_IH
V_OL
V_OH
V_ID
V_OD
t_R
t_F
Parameter
I/O supply voltage
Low-level input voltage
High-level input voltage
Low-level output voltage
High-level output voltage
Differential input voltage
Differential output voltage
Rise time (20 to 80%)
Fall time (20 to 80%)
Conditions
Minimum
3.135
800
2,100
1,450
2,275
100
625
85
85
Typical
3.3
600
800
Maximum
3.465
2,000
V_CCIO
1,650
2,420
2,500
970
325
325
Units
V
mV
mV
mV
mV
mV
mV
ps
ps
Table 45. HyperTransport Specifications
Symbol
Parameter
Conditions
Minimum Typical Maximum Units
V_CCIO
V_OD
V_OCM
V_ID
V_ICM
R_L
I/O supply voltage
Differential output voltage
Output common mode
voltage
Differential input voltage
Input common mode
voltage
Receiver differential input
resistor
R_TT = 100 Ω
2.375
2.5
2.625
V
380
600
820
mV
500
600
700
mV
300
600
900
mV
450
600
750
mV
90
100
110
Ω
Notes to Tables 42 – 45:
(1) Maximum V_OD is measured under static conditions.
(2) When APEX II devices drive LVPECL signals, the APEX II LVPECL outputs must be terminated with a resistor
network.
Capacitance
Table 46 and Figure 40 provide information on APEX II device
capacitance.
Altera Corporation
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