EP2A15 Datasheet, PDF (25/99 Pages) Altera Corporation – Programmable Logic Device Family

Figure 13. Product-Term Logic in ESB
Dedicated Clocks
Global Signals
APEX II Programmable Logic Device Family Data Sheet
48
(1)
MegaLAB Interconnect
65
From
Adjacent
LAB
Local
Interconnect
Note ot Figure 13:
(1) PLL outputs cannot drive data input ports.
9
32
Macrocell
Inputs (1 to 16)
2
CLK[1..0]
16
2
ENA[1..0]
2
CLRN[1..0]
To Row
and Column
Interconnect
Macrocells
APEX II macrocells can be configured individually for either sequential or
combinatorial logic operation. The macrocell consists of three functional
blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX II macrocell.
Altera Corporation
25