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EP2A15 Datasheet, PDF (97/99 Pages) Altera Corporation – Programmable Logic Device Family | |||
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APEX II Programmable Logic Device Family Data Sheet
Table 76. APEX II Selectable I/O Standards Input Adder Delays
Symbol
-7 Speed Grade
-8 Speed Grade
Min
Max
Min
Max
LVCMOS
LVTTL
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
HSTL Class I
HSTL Class II
LVDS
LVPECL
PCML
CTT
3.3-V AGP 1Ã
3.3-V AGP 2Ã
HyperTransport
Differential
HSTL
0.00
0.00
0.10
0.00
0.00
0.00
0.00
â 0.20
â 0.17
â 0.17
â 0.24
â 0.24
â 0.03
â 0.03
â 0.23
â 0.23
â 0.23
0.00
0.00
0.00
â 0.23
â 0.23
0.00
0.00
0.11
0.00
0.00
0.00
0.00
â 0.22
â 0.19
â 0.19
â 0.26
â 0.26
â 0.03
â 0.03
â 0.26
â 0.26
â 0.26
0.00
0.00
0.00
â 0.26
â 0.26
-9 Speed Grade
Unit
Min
Max
0.00
ns
0.00
ns
0.12
ns
0.00
ns
0.00
ns
0.00
ns
0.00
ns
â 0.24
ns
â 0.20
ns
â 0.20
ns
â 0.29
ns
â 0.29
ns
â 0.03
ns
â 0.03
ns
â 0.28
ns
â 0.28
ns
â 0.28
ns
0.00
ns
0.00
ns
0.00
ns
â 0.28
ns
â 0.28
ns
Altera Corporation
97
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