English
Language : 

EP2A15 Datasheet, PDF (74/99 Pages) Altera Corporation – Programmable Logic Device Family
APEX II Programmable Logic Device Family Data Sheet
Table 40. CTT I/O Specifications
Symbol
VCCIO
VTT/VREF
VIH
VIL
II
VOH
VOL
IO
Parameter
Output supply voltage
Termination and input
reference voltage
High-level input voltage
Low-level input voltage
Input pin leakage current
High-level output voltage
Low-level output voltage
Output leakage current
(when output is high Z)
Conditions
0 < VIN < VCCIO
IOH = –8 mA
IOL = 8 mA
GND ð VOUT ð
VCCIO
Minimum
3.0
1.35
VREF + 0.2
–10
VREF + 0.4
–10
Typical
3.3
1.5
Maximum
3.6
1.65
VREF – 0.2
10
VREF – 0.4
10
Units
V
V
V
V
µA
V
V
µA
Table 41. Bus Hold Parameters
Parameter Conditions
1.5 V
VCCIO Level
1.8 V
2.5 V
3.3 V
Units
Min Max Min Max Min Max Min Max
Low sustaining VIN > VIL
current
(maximum)
30
50
70
µA
High sustaining VIN < VIH
current
(minimum)
–30
–50
–70
µA
Low overdrive
current
High overdrive
current
0 V < VIN <
VCCIO
0 V < VIN <
VCCIO
200
–200
300
–300
500 µA
–500 µA
Notes to Tables 20 – 41:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 20 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to - 2 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) VCCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(7) Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power-up.
(9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.
(10) Drive strength is programmable according to values in Table 9 on page 48.
(11) VREF specifies the center point of the switching range.
74
Altera Corporation