EP2A15 Datasheet, PDF (46/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 30. APEX II IOE in DDR Output I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
Output Clock
Enable Delay
Chip-Wide Reset
Logic Array
to Output
Register Delay
Logic Array
to Output
Register Delay
OE Register
D
Q
ENA
CLRN/PRN
OE Register
D
Q
ENA
CLRN/PRN
Output
t_ZX Delay
VCCIO
Optional
PCI Clamp
OE Register
t_CO Delay
VCCIO
Programmable
Pull-Up
Used for
DDR SDRAM
Output Register
D
Q
ENA
CLRN/PRN
Output Register
D
Q
Output
Propagation
Delay
clk
Drive Strength Control
Open-Drain Output
Slew Control
ENA
CLRN/PRN
Bus-Hold
Circuit
The APEX II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations.
APEX II I/O pins transfer data on a DDR bidirectional bus to support
DDR SDRAM at 167 MHz (334 Mbps). The negative-edge-clocked OE
register is used to hold the OE signal inactive until the falling edge of the
clock. This is done to meet DDR SDRAM timing requirements. QDR
SRAMs are also supported with DDR I/O pins on separate read and write
ports.
46
Altera Corporation