EP2A15 Datasheet, PDF (38/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Programmable Speed/Power Control
I/O Structure
APEX II ESBs offer a high-speed mode that supports fast operation on an
ESB-by-ESB basis. When high speed is not required, this feature can be
turned off to reduce the ESB’s power dissipation by up to 50%. ESBs that
run at low power incur a nominal timing delay adder. This Turbo Bit^TM
option is available for ESBs that implement product-term logic or memory
functions. An ESB that is not used will be powered down so that it does
not consume DC current.
Designers can program each ESB in the APEX II device for either high-
speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
The IOE in APEX II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR IOE. Figure 25 shows the structure of the APEX II IOE. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. Both input registers and the latch can be used
for capturing DDR input. Both output registers can be used to drive DDR
outputs. The output enable (OE) register can be used for fast clock-to-
output enable timing. The negative edge-clocked OE register is used for
DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or
bidirectional pins.
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Altera Corporation