EP2A15 Datasheet, PDF (56/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Single-Bit Mode
Single-bit CDS corrects a fixed clock-to-data skew of up to ±50% of the
data bit period, which allows receiver input skew margin (RSKM) to
increase by 50% of the data period. To use single-bit CDS, the
deserialization factor, J, must be equal to the multiplication factor, W. The
combination of allowable W/J factors and the associated CDS training
patterns automatically determine byte alignment (see Table 11).
Table 11. Single-Bit CDS Training Patterns
W/J Factor
10
9
8
7
6
5
4
Single-Bit CDS Pattern
0000011111
000001111
00001111
0000111
000111
00011
0011
Multi-Bit Mode
Multi-bit CDS corrects any fixed clock-to-data skew. This feature enables
flexible board topologies, such as an N:1 topology (see Figure 34), a switch
topology, or a matrix topology. Multi-bit CDS corrects for the skews
inherent with these topologies, making them possible to use.
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Altera Corporation