EP2A15 Datasheet, PDF (84/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 50. APEX II Minimum Pulse Width Timing Parameters
Symbol
t_CH
t_CL
t_CLRP
t_PREP
t_ESBCH
t_ESBCL
t_ESBWP
t_ESBRP
Parameter
Minimum clock high time from clock pin
Minimum clock low time from clock pin
LE clear pulse width
LE preset pulse width
Clock high time
Clock low time
Write pulse width
Read pulse width
Table 51. APEX II External Timing Parameters Note (1)
Symbol
Parameter
Conditions
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_INSUPLL
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Setup time with global clock at IOE input register
Hold time with global clock at IOE input register
Clock-to-output delay with global clock at IOE output register C1 = 35 pF
Clock-to-output buffer disable delay
Clock-to-output buffer enable delay
Slow slew rate = OFF
Setup time with PLL clock at IOE input register
Hold time with PLL clock at IOE input register
Clock-to-output delay with PLL clock at IOE output register C1 = 35 pF
PLL clock-to-output buffer disable delay
PLL clock-to-output buffer enable delay
Slow slew rate = OFF
Note to Table 51:
(1) External timing parameters are factory tested, worst-case values specified by Altera. These timing parameters are
sample-tested only.
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Altera Corporation