EP2A15 Datasheet, PDF (81/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 42 shows the timing model for bi-directional, input, and output
IOE timing.
Figure 42. Synchronous External TIming Model
Dedicated
Clock
OE Register (1)
PRN
DQ
CLRN
Output IOE Register (2)
PRN
DQ
CLRN
Input Register (3)
PRN
DQ
t_XZ
t_ZX
t_OUTCO
Bidirectional Pin
t_INSU
t_INH
CLRN
Notes to Figure 42:
(1) The output enable register is in the IOE and is controlled by the
“Fast Output Enable Register = ON” option in the Quartus II software.
(2) The output register is in the IOE and is controlled by the
“Fast Output Register = ON” option in the Quartus II software.
(3) The input register is in the IOE and is controlled by the “Fast Input Register = ON”
option in the Quartus II software.
Tables 47 through 50 show APEX II LE, ESB, and routing delays and
minimum pulse-width timing parameters for the f_MAX timing model.
Table 47. APEX II f_MAX LE Timing Parameters
Symbol
Parameter
t_SU
LE register setup time before clock
t_H
LE register hold time before clock
t_CO
LE register clock-to-output delay
t_LUT
LUT delay for data-in to data-out
Altera Corporation
81