EP2A15 Datasheet, PDF (9/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
MegaLAB Structure
APEX II devices are constructed from a series of MegaLAB^TM structures.
Each MegaLAB structure contains a group of logic array blocks (LABs),
one ESB, and a MegaLAB interconnect, which routes signals within the
MegaLAB structure. EP2A15 and EP2A25 devices have 16 LABs and
EP2A40 and EP2A70 devices have 24 LABs. Signals are routed between
MegaLAB structures and I/O pins via the FastTrack interconnect. In
addition, edge LABs can be driven by I/O pins through the local
interconnect. Figure 2 shows the MegaLAB structure.
Figure 2. MegaLAB Structure
MegaLAB Interconnect
To Adjacent
LAB or IOEs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
ESB
Local
Interconnect
LABs
Logic Array Block
Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,
LAB control signals, and the local interconnect. The local interconnect
transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.
The Quartus II Compiler places associated logic within a LAB or adjacent
LABs, allowing the use of a fast local interconnect for high performance.
APEX II devices use an interleaved LAB structure, so that each LAB can
drive two local interconnect areas. Every other LE drives to either the left
or right local interconnect area, alternating by LE. The local interconnect
can drive LEs within the same LAB or adjacent LABs. This feature
minimizes the use of the row and column interconnects, providing higher
performance and flexibility. Each LAB structure can drive 30 LEs through
fast local interconnects.
Altera Corporation
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