EP2A15 Datasheet, PDF (51/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Table 10 describes the I/O standards supported by APEX II devices.
Table 10. APEX II Supported I/O Standards
I/O Standard
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X
LVDS
LVPECL
PCML
HyperTransport
Differential HSTL (1)
GTL+
HSTL class I and II
SSTL-2 class I and II
SSTL-3 class I and II
AGP (1× and 2×)
CTT
Type
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
Differential
Differential
Differential
Differential
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Voltage referenced
Input
Reference
Voltage (V_REF)
(V)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.0
0.75
1.25
1.5
1.32
1.5
Output
Supply
Voltage
(V_CCIO) (V)
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
3.3
2.5
1.5
N/A
1.5
2.5
3.3
3.3
3.3
Board
Termination
Voltage
(V_TT) (V)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.5
0.75
1.25
1.5
N/A
1.5
Note to Table 10:
(1) Differential HSTL is only supported on the eight dedicated global clock pins and four dedicated high-speed PLL
clock pins.
f For more information on I/O standards supported by APEX II devices,
see Application Note 117 (Using Selectable I/O Standards in Altera Devices).
APEX II devices contain eight I/O banks, as shown in Figure 31. Two
blocks within the right I/O banks contain circuitry to support high-speed
True-LVDS, LVPECL, PCML, and HyperTransport inputs, and another
two blocks within the left I/O banks support high-speed True-LVDS,
LVPECL, PCML, and HyperTransport outputs. All other standards are
supported by all I/O banks.
Altera Corporation
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