EP2A15 Datasheet, PDF (66/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
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Generic Testing
For more information, see the following documents:
■ Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
■ Jam Programming & Test Language Specification
Each APEX II device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for APEX II
devices are made under conditions equivalent to those shown in
Figure 37. Multiple test patterns can be used to configure devices during
all stages of the production flow. AC test criteria include:
■ Power supply transients can affect AC measurements.
■ Simultaneous transitions of multiple outputs should be avoided for
accurate measurement.
■ Threshold tests must not be performed under AC conditions.
■ Large-amplitude, fast-ground-current transients normally occur as
the device outputs discharge the load capacitances. When these
transients flow through the parasitic inductance between the device
ground pin and the test system ground, significant reductions in
observable noise immunity can result.
Figure 37. APEX II AC Test Conditions
Device
Output
To Test
System
Device input
rise and fall
times < 3 ns
C1 (includes
jig capacitance)
Operating
Conditions
APEX II devices are offered in both commercial and industrial grades.
However, industrial-grade devices may have limited speed-grade
availability.
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Altera Corporation