EP2A15 Datasheet, PDF (8/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 1. APEX II Device Block Diagram
Clock Management Circuitry
ClockLock
IOE
IOE
IOE
IOE
Four-input LUT
for data path and _IOE
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
IOE
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
LUT
Product Term
Memory
IOE
IOE
IOE
IOE
FastTrack
Interconnect
LUT
IOE
IOE
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
Table 4 lists the resources available in APEX II devices.
Table 4. APEX II Device Resources
Device
EP2A15
EP2A25
EP2A40
EP2A70
MegaLAB Rows
26
38
40
70
MegaLAB
Columns
4
4
4
4
ESBs
104
152
160
280
APEX II devices provide eight dedicated clock input pins and four
dedicated fast I/O pins that globally drive register control inputs,
including clocks. These signals ensure efficient distribution of high-speed,
low-skew control signals. The control signals use dedicated routing
channels to provide short delays and low skew. The dedicated fast signals
can also be driven by internal logic, providing an ideal solution for a clock
divider or internally-generated asynchronous control signal with high
fan-out. The dedicated clock and fast I/O pins on APEX II devices can also
feed logic. Dedicated clocks can also be used with the APEX II general-
purpose PLLs for clock management.
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Altera Corporation