EP2A15 Datasheet, PDF (37/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Figure 24. ESB Control Signal Generation
Dedicated
8
Clocks
Fast Global
4
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
INCLKENA
OUTCLKENA
RDEN WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times
of ESBs. The large capacity of ESBs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or distributed RAM blocks. Parameterized functions such
as LPM functions can take advantage of the ESB automatically. Further,
the Quartus II software can implement portions of a design with ESBs
where appropriate.
Altera Corporation
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