EP2A15 Datasheet, PDF(78/99 Page) Altera Corporation – Programmable Logic Device Family

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EP2A15 Datasheet, PDF (78/99 Pages) Altera Corporation – Programmable Logic Device Family

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APEX II Programmable Logic Device Family Data Sheet

Table 46. APEX II Device Capacitance

Symbol

CIN

Parameter

Input capacitance

CINCLK

COUT

Input capacitance on

dedicated clock pin

Output capacitance

Note to Table 46:

(1) See Figure 40.

Conditions

VIN = 0 V,

f = 1.0 MHz

VIN = 0 V,

f = 1.0 MHz

VIN = 0 V,

f = 1.0 MHz

Minimum

Figure 40. APEX II Maximum Input & Output Pin Capacitance

CIN = 10 pF

I/O Bank 1

I/O Bank 2

Maximum

Unit

(1)

I/O Bank 8

CIN = 12 pF

I/O Bank 7

I/O Bank 3

CIN = 7 pF

I/O Bank 4

I/O Bank 6

I/O Bank 5

CIN = 15 pF

Altera Corporation

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