EP2A15 Datasheet, PDF (45/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
When using the IOE for DDR inputs, the two input registers are used to
clock double rate input data on alternating edges. An input latch is also
used within the IOE for DDR input acquisition. The latch holds the data
that is present during the clock high times. This allows both bits of data to
be synchronous to the same clock edge (either rising or falling). Figure 29
shows an IOE configured for DDR input.
Figure 29. APEX II IOE in DDR Input I/O Configuration
Column, Row
or Local
Interconnect
Eight
Dedicated
Clocks
12 Peripheral
Signals
VCCIO
Optional
PCI Clamp
VCCIO
Programmable
Pull-Up
Input Pin to Input
Register Delay
Input Clock
Enable Delay
Input Register
D
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Chip-Wide Reset
Input Register
D
Q
Latch
D
Q
ENA
CLRN/PRN
ENA
CLRN/PRN
Altera Corporation
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from LEs on rising clock edges. These
register outputs are multiplexed by the clock to drive the output pin at a
×2 rate. One output register clocks the first bit out on the clock high time,
while the other output register clocks the second bit out on the clock low
time. Figure 30 shows the IOE configured for DDR output.
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