EP2A15 Datasheet, PDF (47/99 Pages) Altera Corporation – Programmable Logic Device Family

APEX II Programmable Logic Device Family Data Sheet
Zero Bus Turnaround SRAM Interface Support
In addition to DDR SDRAM support, APEX II device I/O pins also
support interfacing with ZBT SRAM devices at up to 200 MHz. ZBT
SRAM blocks are designed to eliminate dead bus cycles when turning a
bidirectional bus around between reads and writes, or writes and reads.
ZBT allows for 100% bus utilization because ZBT SRAM can be read or
written on every clock cycle.
To avoid bus contention, the output clock-to-low-impedance time (t_ZX)
delay ensures that the t_ZX is greater than the clock-to-high-impedance
time (t_XZ). Phase delay control of clocks to the OE/output and input
registers using two general-purpose PLLs enable the APEX II device to
meet ZBT t_CO and t_SU times.
Programmable Drive Strength
The output buffer for each APEX II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL standard has
several levels of drive strength that the user can control. SSTL-3 class I
and II, SSTL-2 class I and II, HSTL class I and II, 3.3-V GTL+, PCI, and
PCI-X support a minimum setting. The minimum setting is the lowest
drive strength that guarantees the I_OH/I_OL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot. Table 9 shows the possible settings for the I/O
standards with drive strength control.
Altera Corporation
47